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74ACT563 Octal Latch with 3-STATE Outputs
November 1988 Revised December 1998
74ACT563 Octal Latch with 3-STATE Outputs
General Description
The ACT563 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The ACT563 device is functionally identical to the ACT573, but with inverted outputs.
Features
s ICC and IOZ reduced by 50% s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to ACT573 but with inverted outputs s Outputs source/sink 24 mA s ACT563 has TTL-compatible inputs
Ordering Code:
Order Number 74ACT563SC Package Number M20B Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for SOIC
IEEE/IEC
Pin Descriptions
Pin Names D0-D7 LE OE O0-O7 Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs Description
FACTTM is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009970.prf
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74ACT563
Functional Description
The ACT563 contains eight D-type latches with 3-STATE complementary outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches.
Function Table
Inputs OE H H H H L L L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change
Internal D X L H X L H X Q X H L NC H L NC
Outputs O Z Z Z Z H L NC
Function
LE X H H L H H L
High-Z High-Z High-Z Latched Transparent Transparent Latched
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT563
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Junction Temperature (TJ) (PDIP) 140C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C
DC Electrical Characteristics
Symbol Parameter VCC (V) VIH VIL VOH Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.25 0.6
TA =-40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4
Units
Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH
V V V
3.76 4.76 0.1 0.1
V V
IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 A VIN = VIL or VIH
0.44 0.44 1.0 2.5 1.5 75 -75
V A A mA mA mA A
IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
5.5 5.5 5.5 5.5 5.5 5.5
4.0
40.0
3
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74ACT563
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 4) tPLH Propagation Delay Dn to On tPHL Propagation Delay Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On tPZH tPZL tPHZ tPLZ Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 2.5 2.0 3.5 2.0 5.5 5.5 6.5 4.5 9.0 8.5 10.5 8.0 2.0 2.0 2.5 1.0 10.0 9.5 11.5 8.5 ns ns ns ns 5.0 2.5 5.5 9.5 2.0 10.5 ns 5.0 3.0 6.5 10.5 2.5 11.5 ns 5.0 3.0 6.0 10.0 2.5 11.0 ns 5.0 Min 3.0 TA = +25C CL = 50 pF Typ 7.0 Max 11.5 TA = -40C to +85C CL = 50 pF Min 2.5 Max 12.5 ns Units
Note 4: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
VCC Symbol Parameter (V) (Note 5) ts th tw Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH 5.0 2.0 3.0 3.0 ns
Note 5: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 1.5 -2.0 4.0 0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 4.5 0 ns ns Units
5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 50.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74ACT563 Octal Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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